Call for Participation

Workshop on Network Processors

February 3, 2002

Cambridge, Massachusetts

To be held in conjunction with

HPCA 8

The 8th International Symposium on High Performance Computer Architecture

February 2-6, 2002


NP1 has successfully concluded.

Please visit NP2 at HPCA9 in Anaheim.

Workshop Objective

As the performance and importance of digital communication networks have increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility and economy requirements, the networking industry has opted to build products around network processors. These processors are programmable yet application-specific; their designs are tailored to efficiently implement communications applications such as: routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. The term network processor is used here in the most generic sense -- from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors.

Network processor design is an emerging field with challenges and opportunities both numerous and formidable. The goal of this one-day workshop is to provide a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices.

Workshop Registration

Travel Information

 

Advance Program

8:00 - 8:55

Registration

8:55 - 9:00

Welcome

9:00 - 10:00

Keynote: Bill Dally, Stanford University

10:00 - 10:30

Break

10:30 - 12:00

Session 1: Hardware and Benchmarking

Gigabit IP Routing on Raw
Saman Amarasinghe, Gleb Chuvpilo and David Wentzlaff, MIT

Benchmarking Network Processors
Prashant R. Chandra, Frank Hady, Raj Yavatkar, Tony Bock, Mason Cabot and Philip Mathew, Intel

A Methodology and Simulator for the Study of Network Processors
Deepak Suryanarayanan, Gregory T. Byrd and
  John Marshall, Cisco Systems, North Carolina State University

12:00 - 1:30

Lunch

1:30 - 3:00

Session 2: Hardware/Software Interface

Design Space Exploration of Network Processor Architectures
Lothar Thiele, Samarjit Chakraborty, Matthias Gries
and Simon Künzli, Swiss Federal Institute of Technology

Architectural Analysis of Cryptographic Applications for Network Processors
Haiyong Xie, Li Zhou, Laxmi Bhuyan,
University of California, Riverside

Advanced Code Generation for Network Processors with Bit Packet Addressing
Jens Wagner and Rainer Leupers,
University of Dortmund, Aachen University of Technology

3:00 - 3:30

Break

3:30 - 5:00

Session 3: Modeling and Benchmarking

A Network Processor Performance and Design Model with Benchmark Parameterization
Mark Franklin and Tilman Wolf,
Washington University in St. Louis

A Benchmarking Methodology for Network Processors
Mel Tsai, Chidamber Kulkarni, Christian Sauer, Niraj Shah and Kurt
Keutzer, University of California at Berkeley, Infineon Technologies

A Modeling Framework for Network Processor Systems
Patrick Crowley and Jean-Loup Baer, University of Washington

5:00 - 5:15

Break

5:15 - 6:15

Panel Session: Network Processors -- Challenges and Implications

Moderator:
Mark Franklin, Washington University in St. Louis

Panelists:
Larry Dennison, Avici Systems
John Freeman, Industry Analyst
Larry Huston, Intel
Keith Morris, AMCC
Dimitrios Stiliadis, Lucent/Bell Labs
John Wakerly, Cisco Systems

 


 

Program Committee:

Patrick Crowley, University of Washington

Mark Franklin, Washington University in St. Louis

Haldun Hadimioglu, Polytechnic University

Marco Heddes, IBM

Nick McKeown, Stanford University

Peter Z. Onufryk, IDT

George Varghese, University of California, San Diego

Raj Yavatkar, Intel
 

Workshop Organizers:

Patrick Crowley, University of Washington (pcrowley@cs.washington.edu)

Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu)

Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu)

Peter Z. Onufryk, IDT (peter.onufryk@idt.com)