Please access the main web page for local copies of the workshop web-sites.

All main program papers are accessible via this page
    Saturday         Sunday         Monday         Tuesday         Wednesday    

Final Program (PDF)

Saturday, February 2, 2002
  CAECW-02: Computer Architecture Evaluation Using Commercial Workloads   local copy
  PACS'02: Power-Aware Computer Systems   local copy
  SAN-1: Workshop on Novel Uses of System Area Networks   local copy
Sunday, February 3, 2002
  Tutorial: Designing Cluster-based Data Centers: Emerging Technologies and Research Challenges
  NSC-1: Workshop on Non-Silicon Computing   local copy
  NP-1: Workshop on Network Processors   local copy
  INTERACT-6: Interaction between Compilers and Computer Architecture   local copy
  Reception
Monday, February 4, 2002

8:45

Introductory remarks from General and Program chairs
9:00

Keynote speaker: Timothy Chou, President, Oracle.com
"The Software Industry: Ten Lessons for Long Life"
10:00

Coffee break
10:30

Energy and thermal management, I
Session chair: Anand Sivasubramaniam, Pennsylvania State University
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage (PDF)
Ed Grochowski, Dave Ayers, and Vivek Tiwari
Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management (PS)
Kevin Skadron, Mircea Stan, and Tarek Abdelzaher
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling (PS)
G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, and M. L. Scott
12:00

Lunch
1:30

Multithreading
Session chair: Yiannakis Sazeides, University of Cyprus
Learning Cross-Thread Violations in Speculative Parallelization for Scalable Multiprocessors (PS)
Marcelo Cintra and Josep Torrellas
Thread-Spawning Schemes for Speculative Multithreading (PS)
Pedro Marcuello and Antonio Gonzalez
Improving Value Communication for Thread-Level Speculation (PS)
J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry
3:00

Coffee break
3:30

Panel discussion
"What will have the greatest impact in 2010: The processor, the memory, or the interconnect?"
Moderator: Timothy Mark Pinkston (USC)
Panelists:
Anant Agarwal (Massachusetts Institute of Technology)
Bill Dally (Stanford University)
Jose Duato (Universidad Politecnica de Valencia, Spain)
Bob Horst (Horst Technology Research)
Yale Patt (University of Texas at Austin)
T. Basil Smith (IBM T. J. Watson Research Center)
6:00

Banquet, New England Aquarium

Tuesday, February 5, 2002

9:00

Parallel Sessions


Potpourri Parallel Session
Session chair: Shubu Mukherjee, Intel
Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs (PS)
Mariko Sakamoto, Larry Brisson, Akira Katsuno, Aiichiro Inoue, and Yasunori Kimura
Tuning Garbage Collection in an Embedded Java Environment (PS)
G. Chen, R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and M. Wolczko


Memory-aware scheduling Parallel Session
Session chair: Mahmut Kandemir, Pennsylvania State University
Fine-grain Priority Scheduling for Memory-Intensive Applications (PS)
Zhichun Zhu, Zhao Zhang, and Xiaodong Zhang
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning (PS)
G. Edward Suh, Srinivas Devadas, and Larry Rudolph
10:00

Coffee break
10:30

Energy and thermal management, II
Session chair: Margaret Martonosi, Princeton University
The Minimax Cache: An Energy-Efficient Framework for Media Processors (PS)
Osman S. Unsal, Israel Koren, C. Mani Krishna, and Csaba Andras Moritz
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach (PS)
S. Gurumurthi, A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M. Kandemir, T. Li and L. K. John
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay (PS)
Se-Hyun Yang, M. D. Powell, Babak Falsafi and T. N. Vijaykumar
12:00

Lunch
1:30

Latency tolerance and caches
Session chair: Steve Lumetta, University of Illinois at Urbana-Champaign
Non-vital Loads (PDF)
Ryan Rakvic, Bryan Black, Deepak Limaye, and John P. Shen
Let's Study Whole-Program Cache Behaviour Analytically (PS)
Xavier Vera and Jingling Xue
Two Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PS)
Perry Wang, Hong Wang, Jamison Collins, Edward Grochowski, Ralph Kling, and John Shen
Quantifying Load Stream Behavior (PS)
Suleyman Sair, Timothy Sherwood, and Brad Calder
3:30

Coffee break
4:00

Speculation and prediction
Session chair: Brad Calder, University of California at San Diego
Modeling Value Speculation (PS)
Yiannakis Sazeides
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches (PS)
Martin Kampe, Per Stenstrom, and Michel Dubois
Power Issues Related to Branch Prediction (PS)
Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco Barcella, and Mircea Stan
7:30

Work-in-progress
Organizers: Bruce Childers (University of Pittsburgh), Koji Inoue (Fukuoka University), Sally A. McKee (University of Utah), Martin Schulz (Technische Universitat Munchen).

Wednesday, February 6, 2002

9:00

Keynote speaker: David A. Patterson, Pardee Chair of Computer Science, University of California at Berkeley
"Recovery Oriented Computing: A New Research Agenda for a New Century"
10:00

Coffee break
10:30


Parallel Sessions


Multiprocessor systems  - Parallel Session
Session chair: Babak Falsafi, Carnegie Mellon University
Bandwidth Adaptive Snooping (PS)
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters (PDF)
Peter Jamieson and Angelos Bilas
User-Level Communication in Cluster-Based Servers (PS
E. V. Carrera, S. Rao, L. Iftode, and R. Bianchini


Pipelining and microarchitecture  - Parallel Session
Session chair: Gary Tyson, University of Michigan
Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files (PS)
Mary D. Brown and Yale N. Patt
Loose Loops Sink Chips (PS)
Eric Borch, Eric Tune, Srilatha Manne, and Joel Emer
Evaluation of a Multithreaded Architecture for Cellular Computing (PS)
Calin Cascaval, Jose Castanos, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, Jose Moreira, Karin Strauss, and Henry S. Warren, Jr.

12:00

End of conference wrap-up