Dharma P. Agrawal, Univ. of Cincinnati
Laxmi N. Bhuyan, Univ. of California, Riverside
Yale Patt, Univ. of Texas, Austin
Jean-Luc Gaudiot, Univ. of California, Irvine
Nader Bagherzadeh, Univ. of California, Irvine
Rajiv Gupta, Univ. of Arizona
Sarita Adve, Univ. of Illinois, Urbana-Champaign
David Albonesi, Univ. of Rochester
Eduard Ayguade, UPC, Barcelona, Spain
Ricardo Bianchini, Rutgers Univ.
Angelos Bilas, Univ. of Crete
Gregory T. Byrd, North Carolina State Univ.
Frederic T. Chong, Univ. of California, Davis
Bill Dally, Stanford Univ.
Michel Dubois, Univ. of Southern California
Hans Eberle, Sun Microsystems
Kanad Ghose, State Univ. of New York
Antonio González, UPC/Intel, Barcelona, Spain
José González, Intel, Barcelona, Spain
Erik Hagersten, Uppsala Univ.
Mark Heinrich, Univ. of Central Florida
Stefanos Kaxiras, Agere Systems
Ruby B. Lee, Princeton Univ.
Daniel Litaize, IRIT, Toulouse
Olav Lysne, Simula Research Laboratory, Oslo
José F. Martínez, Cornell Univ.
Margaret Martonosi, Princeton Univ.
Sally McKee, Cornell Univ.
Pankaj Mehra, Hewlett-Packard
Jaime H. Moreno, IBM T.J. Watson Research Center
Trevor Mudge, Univ. of Michigan, Ann Arbor
Shubu Mukherjee, Intel
Ashwini Nanda, IBM T.J. Watson Research Center
Vijay Narayanan, Pennsylvania State Univ.
Mario Nemirovsky, Kayamba
Dhabaleswar K. Panda, Ohio State Univ.
Li-Shiuan Peh, Princeton Univ.
Lawrence Rauchwerger, Texas A&M Univ.
Gabby Silberman, IBM T.J. Watson Research Center
Anand Sivasubramaniam, Pennsylvania State Univ.
Gurindar S. Sohi, Univ. of Wisconsin, Madison
Evan Speight, Cornell Univ.
Josep Torrellas, Univ. of Illinois, Urbana-Champaign
David Wood, Univ. of Wisconsin, Madison
Qing Yang, Univ. of Rhode Island
Mazin Yousif, Intel
Local Arrangements Chair
Institutional Relations Chairs
The International Symposium on High-Performance Computer Architecture
provides a high quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field. Authors are
invited to submit full papers on all aspects of high-performance computer
architecture. Topics of interest include, but are not limited to:
- Processor architectures
- Cache and memory architectures
- Parallel computer architectures
- Impact of VLSI scaling techniques
- Novel architectures for emerging applications
- Power-efficient architectures
- High-availability architectures
- High-performance I/O architectures
- Embedded and reconfigurable architectures
- Real-time architectures
- Interconnect and network interface architectures
- Network processor architectures
- Innovative hardware/software trade-offs
- Simulation and performance evaluation
- Benchmarking and measurements
Please check the following web site for paper submission information:
The submission should not exceed 12 pages in IEEE double column format.
Papers that exceed the length limit or that cannot be viewed using Adobe
Acrobat Reader (version 3.0 or higher) may not be reviewed. The official
submission deadline is July 14, 2003 (9pm Pacific Time, USA).
An automatic extension of one week will be given without request. No further
extensions will be given. Papers may be submitted for blind review at the
option of the authors. Please indicate whether the paper is a student paper
for best student paper nominations. Please submit proposals for workshops
to the workshops chair by July 14, 2003.
Paper submission deadline: July 14, 2003 (closed)
Workshop proposals due: July 14, 2003 (closed)
Author notification: Oct. 6, 2003
Camera ready copy due: Nov. 3, 2003